Neuromorphic computer

ABSTRACT

A neuromorphic computing device utilizing electronics to perform the function of neurons and synaptic connections. The invention provides variable resistance circuits to represent interconnection strength between neurons and a positive and negative output circuit to represent excitatory and inhibitory responses, respectively. The invention provides advantages over software-based neuromorphic computing methods.

STATEMENT OF GOVERNMENT INTEREST

The invention described herein may be manufactured and used by or for the Government for governmental purposes without the payment of any royalty thereon.

BACKGROUND OF THE INVENTION

This invention relates generally to the field of computer architectures modeled on the function of the brain. More specifically, the present invention relates to a computer architecture using modern electronics to perform the function of neurons and synaptic connections.

The amazing computing power of the brain originates thanks to its highly parallelized interconnectivity amongst neurons through synaptic connections. The synaptic connection plays an important role in brain activity as these connections can be strengthened or weakened as the brain learns and knowledge is stored within the system [2]. Neuron behavior has been characterized as an adding system that provides an output based on the sum of all inputs, or synapse outputs, and its connectivity to other neurons [1]. In addition, the amount of information or knowledge a neuromorphic computer can retain depends on the number neurons and synaptic connections within the system. For example, the brain of an ant is said to contain approximately 300,000 neurons [3].

The natural ability of the brain to perform a high number of complex functions in parallel that to date are unmatched by the fastest most powerful supercomputers represents a great technological engineering challenge. Neuromorphic computers promise to provide artificial machines the ability to perform complex functions by mimicking the brain's engineering. Software based implementations of neuromorphic computing have demonstrated the feasibility of mimicking brain functionality [1]. However, software based implementations of neuromorphic computing require high performance computers and super computers that in turn make usage of such applications in everyday life impractical specially within mobile and/or low cost systems.

What is lacking, therefore, is the development of hardware based neuromorphic computer that will enable a technological breakthrough with the implementation of brain functionality within systems that are built based on the engineering principles of the brain. Such a hardware based neuromorphic computer would require a neuromorphic hardware architecture that mimics the brain's synaptic and neuron functionality employing electronic devices to represent synaptic and neuron characteristic behavior. Given the large number of neurons and synaptic connections (approximately 1,000 synaptic connections per neuron) required to design systems capable of mimicking practical brain functionality such as image recognition, it is important for the electronic devices to be small in order to be fabricated within a small physical area as computer microprocessors are fabricated today.

OBJECTS AND SUMMARY OF THE INVENTION

The present invention provides an apparatus to perform human brain-like computing functions.

It is an object of the present invention to provide an apparatus that overcomes the limitations of software-based methods to perform human brain-like computing functions.

It is another object of the present invention, then, to provide an electronic means to perform excitatory and inhibitory responses.

It is another object of the present invention to provide an apparatus that performs the functions of neurons and synaptic connections through electronic means.

It is a further object of the present invention to provide an electronic means for performing the functions of neurons and synaptic connections which is amenable to high density fabrication.

Briefly stated, the present invention provides an apparatus for human brain-like (i.e., neuromorphic) computing utilizing electronics to perform the function of neurons and synaptic connections. The invention provides variable resistance circuits to represent interconnection strength between neurons and a positive and negative output circuit to represent excitatory and inhibitory responses, respectively. This approach has definite advantages over software-based neuromorphic computing methods.

The above, and other objects, features and advantages of the present invention will become apparent from the following description read in conjunction with the accompanying drawings, in which like reference numerals designate the same elements.

REFERENCES

-   [1] J. Lawrence and S. Luedeking, “Introduction to Neural Networks,”     California Scientific software, Grass Valley, Calif., 1991. -   [2] G. Bi and M. Poo, “Synapti Modification by Correlated Activity:     Hebb's Postulate Revisited,” Annual Review of Neuroscience,     24 (2001) 139-66 -   [3] Science blogging the intersection between biology and     technology,     <http://www.greythumb.org/blog/index.php?/archives/262-Number-of-neurons-in-an-ants-brain.html>,     2007. -   [4] L. O. Chua, “Memristor—The Missing Circuit Element,” IEEE     Transactions on Circuits Theory, 18 (1971) 507-519. -   [5] Wikipedia, the free encyclopedia,     “MOSFET,”<http://en.wikipedia.org/wiki/MOSFET>, 2009.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 depicts the I-V electrical characterization results described by Eqn (1), specifically, nfet drain-to-source current (Ids) vs. drain-to-source voltage (Vds) for several values of Vgs-Vth; the boundary between linear (Ohmic) and saturation (active) modes is indicated by the upward curving parabola.

FIG. 2 depicts the nfet channel conductance for the same biasing voltage conditions indicated in FIG. 1.

FIG. 3 depicts variable resistive equivalent circuit element that can be achieved with a MOSFET or memristor devices.

FIG. 4 depicts a CMOS inverter.

FIG. 5 depicts a CMOS inverter output voltage (Vout) versus input signal (Vin) where Vth=0 and −1V for the nfet and pfet devices and Vmax=2 V and Vmin=−2 V respectively.

FIG. 6 depicts a synaptic system employing a MOSFET (a), memristor (b), and the simplified synaptic circuit representation (c).

FIG. 7 depicts the convergence of multiple synaptic outputs at the floating adding node and their combined response is fed to the next neuron synaptic layer of the neuromorphic computing architecture.

FIG. 8 depicts how the convergence of multiple synaptic outputs at the adding neuron where their relative contribution (the adding of all post-synaptic output potentials) will cause the single MOSFET neuron to fire as long at the overall synaptic contribution is above its threshold potential, and how the neuron output. Vo will be fed to the next synaptic layer of the neuromorphic computing architecture.

FIG. 9 depicts a neuromorphic architecture implementation with floating adding neurons.

FIG. 10 depicts a neuromorphic computing architecture implementation employing thresholding neurons.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The basic building block of the neuromorphic computer is the synapse circuit. A synapse circuit requires (1.) a variable resistance circuit to represent the interconnection strength between neurons and (2.) a positive/negative output circuit to represent excitatory and inhibitory responses.

Variable Resistor Circuit

In the present invention, a variable resistor is obtained by biasing an n-channel field effect transistor (nfet) device in such a way that it operates within the linear region. This functionality can also be achieved with a memristor [4] device. In the linear or Ohmic mode region, the drain source current of the nfet behavior can be modeled as [5]:

$\begin{matrix} {I_{DS} = {\mu_{n}C_{OX}\frac{W}{L}\left( {{\left( {V_{GS} - V_{th}} \right)V_{DS}} - \frac{V_{DS}^{2}}{2}} \right)}} & (1) \end{matrix}$

where IDS is the drain to source current, μn is the electron mobility, Cox is the gate oxide capacitance, W and L are the width length of the device, Vth is the nfet's threshold voltage, and VGS and VDS are the gate-to-source and drain-to-source bias voltages. For the nfet transistor to operate within the linear region (cut-off or sub-threshold or weak inversion mode), the gate biasing potential must be less that the threshold voltage, VGS<Vth. From Eqn. (1) the channel variable resistance, R, or conductance, G is defined as:

$\begin{matrix} {{G\left( {V_{GS},V_{th},V_{DS}} \right)} = {\frac{1}{R\left( {V_{GS},V_{th},V_{DS}} \right)} = {\mu_{n}C_{OX}\frac{W}{L}\left( {V_{GS} - V_{th} - \frac{V_{DS}}{2}} \right)}}} & (2) \end{matrix}$

therefore, Eqn. (1) can be rewritten as:

$\begin{matrix} {I_{D} = {{{G\left( {V_{GS},V_{th},V_{DS}} \right)}*V_{DS}} = {\frac{1}{R\left( {V_{GS},V_{th},V_{DS}} \right)}*V_{DS}}}} & (3) \end{matrix}$

FIG. 1 displays the I-V electrical characterization results described by Eqn (1) for a symmetric nfet device. Nfet drain-to-source current (Ids) vs. drain-to-source voltage (Vds) for several values of Vgs-Vth is depicted. The boundary between linear (Ohmic) and saturation (active) modes is indicated by the upward curving parabola. Still referring to FIG. 1, one can observe that the linear region, bounded by the pinch-off dashed line, where VGS>Vth and VDS<(VGS-Vth), provides a variable resistive behavior that is a function of gate, drain, and source node and threshold voltage biases as described by Eqn (2). From the electrical characterization results displayed in FIG. 1, it is possible to calculate the conductance G, which is by definition the first derivative of the drain-to-source current with respect to the drain-to-source voltage and the results are shown in FIG. 2.

Referring to FIG. 2 depicts the nfet channel conductance for the same biasing voltage conditions outlined in FIG. 1. From the figure, we can observe that the nfet device displays a range of conductance that is proportional to the gate, drain, and source potential biases.

Referring to FIG. 3 depicts how the variable resistive equivalent circuit element 100 can be achieved with a MOSFET 110 or memristor 120 devices. FIG. 3 also depicts the electrical equivalent diagram for a MOSFET device 110 operated within the linear region and a memristor device 120 to the electrical symbol of a variable resistor 100. This variable conductance, or its inverse the resistance, can be used to control the connection strength between synapses and neuron circuitry.

Positive/Negative Output Potential Circuit Element

Referring to FIG. 4, the present invention re-create the positive and negative (excitatory and inhibitory) potential outputs of a synaptic system by employing a common CMOS inverter circuit 130 operating along its transition region. A pfet device 150 (distinguished by the black notch on its gate 140) is connected to an nfet 160 device in series. Both devices receive the same input, and based on the input potential, the inverter circuit 130 will output either Vmax or Vmin. For example, if the input potential is 0 volts, the nfet device 160 will be in the off state meaning the input potential is below its threshold voltage and no conducting channel is formed under the gate. On the other hand, at 0 volts, the pfet device 150 is switched on given that its threshold potential is negative. Therefore, for a zero input voltage the output of the inverter 130 is Vmax as Vout will be shorted to Vmax through the channel under the gate 140 for the pfet device 150.

The present invention needs to operate the inverter circuit 130 along its transition region to achieve positive (Vmax) and negative (Vmin) potential outputs that will resemble post-synaptic behavior. Since the inverter circuit 130 of FIG. 4, works in saturation mode, meaning that Vmax and Vmin (VDS) are both greater in magnitude than (VGS-Vth), transistor current saturation equations describe its transition characteristics. For an nfet device, ignoring channel length modulation, the drain current is modeled as for the nfet as [4] (for the pfet reverse current flow direction):

$\begin{matrix} {I_{DS} = {\frac{\mu_{n}C_{OX}}{2}\frac{W}{L}\left( {V_{GS} - V_{th}} \right)^{2}}} & (4) \end{matrix}$

Referring to FIG. 5, depicts a CMOS inverter output voltage (Vout) versus input signal (Vin) where Vth=0 and −1V for the nfet and pfet devices and Vmax=2 V and Vmin=−2 V respectively. For nfet and pfet devices with 0 and −1 V threshold voltages, the CMOS inverter transition region can be simulated using Equation (4), and the simulation results are displayed. Still referring to FIG. 5, one can observe that it is possible to obtain tunable range of output potentials (positive or negative) as function of a single input bias potential. This particular functionality is important in the present invention because its synaptic system is capable of both positive and negative output potentials. The simulation results displayed in FIG. 5 can be used to create a compact linear model that is used to describe the inverting circuit as:

V _(OUT)=(−4)*V _(in)+2V

where Vin is the input to the inverting circuit.

Synaptic System

In the present invention the synaptic system employs the variable resistor and inverter circuit elements described previously. Referring to FIG. 6 describes the complete synaptic system by way of a circuit representation of a synapse using a transistor 170 and alternately a memristor 180. The simplified circuit element form 180 will be employed when designing the neuromorphic network. From FIG. 6, one can observe that the output of the synaptic system is a function of the Vm potential that will either strengthen, weaken, or completely cut-off the connection between the synapse input and the CMOS inverting circuit 130 (see also FIG. 4, 130) operating within its transition bias point range.

The synapse output (SO) can be modeled as:

SO(SI,Vm)=ƒ[I(Vm)*R]  (6)

Where ƒ represents the transfer function of the CMOS inverter 130, i.e. described in Eqn. (5), I(Vm) is current across the transistor channel (or transistor channel operating in the linear region as a variable resistance), and R is a resistor used to reset the synapse. For example, for synaptic inputs between 0 and 1 V, as shown in FIG. 5, Eqn. (6) will range from 2 to −2 V approximately as a function of the resistive element R(Vm). Equations (5) and (6) can be combined to obtain:

S O(S I, Vm) = −4 * [I(Vm) * R] + 2V ${I({Vm})} = {\mu_{n}C_{OX}\frac{W}{L}\left( {{\left( {V_{m} - V_{th}} \right)S\; I} - \frac{S\; I^{2}}{2}} \right)}$ ${S\; {O\left( {{S\; I},{Vm}} \right)}} = {{{- 4}*\left\lbrack {\mu_{n}C_{OX}\frac{W}{L}\left( {{\left( {V_{m} - V_{th}} \right)S\; I} - \frac{S\; I^{2}}{2}} \right)R} \right\rbrack} + {2V}}$

where SI is the input to the synapse in voltage units, V_(m) is a biasing weight voltage of the transistor, W is the width of the gate of the transistor, L is the length of the gate of the transistor, C_(ox) is the gate oxide capacitance of the transistor, R is the value of a biasing resistor used to control the potential output of the synapse, V_(th) is the threshold voltage of the transistor, and μ_(n) is electron mobility of the transistor.

Adding Node and Single Transistor Adding Neuron Neuromorphic Architecture Referring to FIG. 7 and FIG. 8 concurrently, the implementation of the neuron functionality in the present invention is performed with an adding node 200 and/or a single transistor. FIG. 7 depicts multiple synaptic outputs converging at multiple floating adding nodes 200 and their combined response is fed to the next neuron synaptic layer of the neuromorphic computing architecture. The adding node 200 is the physical connection where all post-synaptic outputs converge. As the synaptic outputs converge, they will increase or decrease the potential at the floating neuron adding node 200. As depicted in FIG. 8, multiple synaptic outputs converge at the adding neuron 200 where their relative contribution (the adding of all post-synaptic output potentials) will cause the single MOSFET neuron 210 to fire as long at the overall synaptic contribution is above its threshold potential. The neuron output Vo will be fed to the next synaptic layer of the neuromorphic computing architecture. Thus, the resulting added potential will become the input to the following synaptic layer. In addition, if the neuron adding node where connected to the gate of an nfet transistor, and if the total combined potential at the adding node is greater than the threshold voltage, Vth, of the MOSFET transistor, the output of the neuron will be Vo=Vn. Otherwise, the neuron won't have an output (the neuron won't fire) as shown in FIG. 8.

Referring to FIG. 9 depicts an example of a neuromorphic architecture implementation with floating adding neurons. Successive layers of synapse circuits are functionally depicted as being arranged horizontally, from left to right. The number of synapse circuits in each successive layer decreases by a factor of two owing to the effect of floating adding neurons. Computer simulations based on the physical principles described above demonstrate the feasibility of the neuromorphic architectures described herein. One skilled in the art would appreciate that variations of neuromorphic architectures can be constructed employing transistors, memristors, and inverter circuits coupled to floating node neurons or thresholding neurons to perform computations as described previously. FIG. 10 depicts another example of a neuromorphic implementation that demonstrates how a computing architecture can be implemented with floating node and thresholding neurons.

Having described preferred embodiments of the invention with reference to the accompanying drawings, it is to be understood that the invention is not limited to those precise embodiments, and that various changes and modifications may be effected therein by one skilled in the art without departing from the scope or spirit of the invention as defined in the appended claims. 

1. A neuromorphic computing device, comprising: at least one input; at least one output; a plurality of synapse circuits electrically interconnecting said at least one input to said at least one output; said plurality of synapse circuits being configured in successive layers, each successive layer having at least one synapse circuit; wherein a subsequent said successive layer possesses fewer said synapse circuits than an immediately prior said successive layer; and a plurality of floating voltage adding nodes; wherein each of said plurality of floating voltage adding nodes electrically connects and sums outputs corresponding to at least two of said plurality of synapse circuits of any one said successive layer.
 2. The neuromorphic computing device of claim 1, wherein said synapse circuit further comprises an input; an output; a variable resistance element having an input and an output; and an output circuit having an input and an output; wherein said input of said synapse circuit is electrically connected to said input of said variable resistance element; said output of said variable resistance element is electrically connected to said input of said output circuit; said output of said output circuit is electrically connected to said output of said synapse circuit; and wherein said variable resistance element controls the connection strength between said synapse circuits and said floating voltage adding nodes.
 3. The neuromorphic computing device of claim 2, wherein said variable resistance element further comprises a transistor biased in its linear operating region.
 4. The neuromorphic computing device of claim 2, wherein said variable resistance element further comprises a memristor.
 5. The neuromorphic computing device of claim 2, wherein said output circuit is an inverter circuit, said inverter circuit being responsive to an input so as to produce a minimum and a maximum output voltage.
 6. The neuromorphic computing device of claim 5, wherein said inverter circuit comprises a p-field effect transistor having a gate, a drain, and a source; and a n-field effect transistor having a gate, a drain and a source; wherein said gate of said p-field effect transistor is electrically connected to said gate of said n-field effect transistor and to said input of said inverter circuit; and said source of said p-field effect transistor is electrically connected to said drain of said n-field effect transistor and to said output of said inverter circuit.
 7. The neuromorphic computing device of claim 1, wherein said subsequent said successive layer possesses half as many said synapse circuits than an immediately prior said successive layer.
 8. The neuromorphic computing device of claim 6 having said variable resistance element comprising said transistor biased in its linear operating region, wherein said output of said synapse circuit outputs a signal SO(SI, Vm) according to the relationship ${S\; {O\left( {{S\; I},{Vm}} \right)}} = {{{- 4}*\left\lbrack {\mu_{n}C_{OX}\frac{W}{L}\left( {{\left( {V_{m} - V_{th}} \right)S\; I} - \frac{{SI}^{2}}{2}} \right)R} \right\rbrack} + {2V}}$ wherein SI is the input to said synapse in voltage units; V_(m) is a biasing weight voltage of said transistor; W is the width of said gate of said transistor; L is the length of said gate of said transistor; C_(ox) is the gate oxide capacitance of said transistor; R is the value of a biasing resistor used to control the potential output of said synapse; V_(th) is the threshold voltage of said transistor; and μ_(n) is electron mobility of said transistor. 